Thin-film storage transistors in a 3-dimensional array or nor memory strings and process for fabricating the same

ABSTRACT

A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers. In this configuration, the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This present application relates to and claims priority of U.S. provisional patent application (“Related Application I”), Ser. No. 63/072,771, entitled “Thin-film Storage Transistors in a 3-Dimensional NOR Memory Array and Process for Fabricating The Same,” filed on Aug. 31, 2020.

The present application is also related to (i) U.S. provisional patent application (“Related Application II”), Ser. No. 63/054,750, entitled “Methods for Fabricating a 3-Dimensional Memory Structure of NOR Memory Strings,” filed on Jul. 21, 2020; (ii) U.S. patent application (“Related Application III”), Ser. No. 16/510,610, entitled “Fabrication Method For a 3-Dimensional NOR Memory Array,” filed on Jul. 12, 2019; (iii) U.S. patent application (“related Application IV”), Ser. No. 16/894,624, entitled “3-Dimensional NOR Memory Array With Very Fine Pitch: Device and Method,” filed Jun. 5, 2020; and (iv) U.S. provisional patent application (“Related Application V”), Ser. No. 62/950,390, entitled “Process For Preparing A Channel Region Of A Thin-Film Transistor In A 3-Dimensional Thin-Film Transistor Array,” filed on Dec. 19, 2019.

The disclosures of Related Applications I-V (collectively, the “Related Applications”) are hereby incorporated by reference in their entireties.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to memory integrated circuits and processes for their manufacturing. In particular, the present invention relates to thin-film storage transistors in a 3-dimensional memory structure formed on a planar surface of a semiconductor substrate and processes for their manufacturing.

2. Discussion of the Related Art

High density memory arrays, e.g., 3-dimensional arrays of NOR memory strings (“3-D NOR memory arrays”), are disclosed in, for example, U.S. Patent Application Publication 2017/0092371A1 (“Structural Reference I”), entitled “Capacitive-Coupled Non-Volatile Thin-film Transistor Strings in Three-Dimensional Arrays,” and U.S. Patent Application Publication 2018/0366489A1 (“Structural Reference II”), entitled “3-Dimensional NOR Memory Array Architecture and Methods for Fabrication Thereof.” The disclosures of Structural References I and II (collectively, “Structural References”) are hereby incorporated by reference in their entireties. In addition to providing high memory density and high capacity, these 3-D NOR memory arrays are memory circuits operating at highly desirable speeds that rival conventional memory circuits of much lower circuit densities and significantly higher power dissipation (e.g., as dynamic random-access memories or “DRAMs”).

In some of the Related Applications, forming the channel regions of thin-film storage transistors in a 3-D NOR memory array is challenging, as device and process complexities (e.g., highly constraining thermal budget) restrict the choices of available reagents and materials.

SUMMARY

According to one embodiment of the present invention, thin-film storage transistors in a 3-D NOR memory array are structured to allow their channel regions to be formed at an early stage of its fabrication process. The fabrication processes for these thin-film storage transistors have advantages (e.g., fewer photo-lithographical steps) over some of the processes disclosed in the Related Applications. For example, according to one embodiment, a process for fabricating the 3-D memory array of the present invention has fewer masking steps, as it requires less global word line layers. According to another embodiment, by judiciously forming the gate electrodes before forming the source and drains regions, the process obviates safeguards intended to ensure minimal dopant diffusion between the source or drain regions and the channel regions. The thin-film storage transistors of the present invention may sustain higher currents relative to those disclosed in the Structural References without compromising memory density.

According to one embodiment of the present invention, a thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers. In this configuration, the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor. The thin-film storage transistor may further include second and third conductors adjacent and in electrical contact with the second and third semiconductor layers, respectively, to serve as shunts to reduce resistivity in the source and drain regions. The first conductor serves as a gate electrode for the thin-film storage transistor.

In one embodiment, the charge storage layer is a multi-layer including as components a tunneling dielectric layer, a charge-trapping layer and a blocking dielectric layer. In one embodiment, at least a portion of the charge-storage layer is provided in a recessed portion of the first semiconductor region from the opening. The charge-storage layer may surround the gate electrode providing a large capacitance to achieve low variations in threshold voltages among the thin-film storage transistors in the memory array. In another embodiment, the charge-storage layer may be divided into multiple sections (e.g., two semi-annular sections) each providing charge storage to a separate thin-film storage transistor.

In one embodiment, multiple thin-film storage transistors share the gate electrode in the opening, the opening being a vertical via through the active layers and the dielectric layers. When at least a portion of the charge-storage layer is provided in a recessed portion of the first semiconductor region of each active layer, the charge-storage layers of the thin-film storage transistors sharing the gate electrode may be separated from each other. The thin film storage transistors in the via are part of a memory array consisting of a regular array of such thin-film storage transistors situated in numerous like vias. The thin-film storage transistors formed on the same active layer may be organized as NOR memory strings.

Global word lines may be formed to connect to the gate electrodes to communicate word line signals. In one embodiment, the global word lines are formed exclusively above the memory array. In that configuration, design constraints on the global word lines are relaxed relative to providing at least some of the global word lines between the memory array and the planar surface of the semiconductor substrate.

According to one embodiment of the present invention, a process for forming the thin-film storage transistor of the present invention may include (i) providing over the planar surface numerous active layers each separated from another by a dielectric layer, each active layer includes numerous sections each having a first semiconductor region of a first conductivity type; (ii) providing in each section a charge-storage layer and a conductor by (a) forming multiple vias, wherein each via passes through the first semiconductor region of one of the sections in each active layer and the dielectric layers adjacent thereto, wherein each via extends along a direction substantially normal to the planar surface of the semiconductor substrate; (b) forming the charge storage layer conformally over the sidewalls of the via; and (c) forming the conductor by filling the via with a conductive material; and (iii) providing in each section second and third semiconductor regions of a second conductivity type, wherein each of the second and third semiconductor region are provided adjacent and in electrical contact with the first semiconductor region of the section.

In one embodiment, the process includes forming above the active layers a layer of interconnection conductors each connecting to one or more of the conductors in the filled vias.

In one embodiment, the charge-storage layer includes depositing a tunnel dielectric layer, a charge-trapping layer, and a blocking dielectric layer. The charge storage layer may be conformally formed over the sidewalls of the vias using: (a) from the sidewalls of each via, recessing each first semiconductor region of the active layers using an etchant selective to the dielectric layers to forma a cavity between the dielectric layers adjacent to the first semiconductor region; (b) forming the tunnel dielectric layer by a conformal deposition of a tunnel dielectric material to coat both the sidewalls of the via and the walls of the cavities; (c) forming the charge-trapping layer by a conformal deposition of a charge-trapping material to coat the sidewalls of the via and to fill the cavities; (d) using an anisotropic etch to remove the charge-trapping material from the sidewalls of the via; and forming the blocking dielectric layer by a conformal deposition of a blocking dielectric material. In this configuration, the charge-storage layers of the thin-film storage transistors formed sharing a common electrode would be separated from each other.

In one embodiment, the forming the conductor by filling the via with a conductive material may be carried out by: (i) filling the via with a sacrificial material in the via after the charge-storage layer is formed; (ii) patterning and removing from the via a portion of the sacrificial material to form a slit that exposes portions of the charge-storage layer; (iii) removing the exposed portions of the charge-storage layers to divide the charge-storage layer on the sidewalls of the via into isolated sections; (iv) filling the slit with a dielectric material; (v) removing all remaining sacrificial material from the via; and (vi) filling the via with the conductive material. Using this process, the charge-storage layer within the via are divided into more separate sections than the number of active layers, each section being provided to a separate one of the thin-film storage transistors. As a result, a higher storage density can be achieved.

In one embodiment, the second and third semiconductor regions may be provided in each section by (i) forming trenches through the active layers and their adjacent dielectric layers, the trenches each extending in depth substantially normal to the planar surface of the semiconductor surface; (ii) accessing from the sidewalls of the trenches, recessing the first semiconductor layer from the sidewalls using an etchant selective to the dielectric layers so as to form cavities between adjacent dielectric layers; (iii) filling the cavities by depositing into the cavities a semiconductor material of the second conductivity type to form the second and third semiconductor regions of each section; and (v) filling the trenches with a dielectric material.

By forming the common conductors in the vias prior to forming the second and third semiconductor regions, an elevated process step in forming the conductor would not cause dopants in the second and third semiconductor regions to diffuse into the first semiconductor region of the thin-film semiconductor region. As a result, higher diffusivity dopants, such as phosphorus may be used. Otherwise, arsenic is preferred. In one embodiment, however, creating the trenches and recessing the first semiconductor regions may be carried out prior to forming the common conductors in the vias. In that embodiment, a sacrificial material may be used to fill the cavities adjacent the first semiconductor regions and replaced subsequent to forming the common conductors by the second and third semiconductor regions.

The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings are schematic representations of various embodiments of the present disclosure and are not meant to be actual views of any particular component, structure, or device. The drawings are not to scale, and the thickness and dimensions of some layers may be exaggerated for clarity. Like reference numerals refer to like components throughout.

FIG. 1 shows isometric and expanded schematic views of memory structure 100 at an initial step of a fabrication process for a 3-D NOR memory array, in accordance with one embodiment of the present invention.

FIG. 2 shows isometric and expanded schematic views of memory structure 100 of FIG. 1, after recessing the silicon layers 10, in accordance with one embodiment of the present invention.

FIG. 3 shows isometric and expanded schematic views of resulting memory structure 100, after deposition and isotropic etching of heavily-doped silicon layers 50, in accordance with one embodiment of the present invention.

FIG. 4 shows isometric and expanded schematic views of resulting memory structure 100, after anisotropic etching of conductive material 60, in accordance with one embodiment of the present invention.

FIG. 5 shows an isometric schematic view of resulting memory structure 100, after an etch-back or CMP of dielectric material 70, in accordance with one embodiment of the present invention.

FIG. 6 shows isometric and expanded schematic views of resulting memory structure 100, after etching of vias 80, in accordance with one embodiment of the present invention.

FIG. 7 shows isometric and expanded schematic views of resulting memory structure 100, after filling of vias 80 by conductive material 95, in accordance with one embodiment of the present invention.

FIG. 8 shows a portion of resulting memory structure 100 with the passivation layer and dielectric layers 20 removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory arrays, in accordance with one embodiment of the present invention.

FIG. 9 shows isometric and expanded schematic views of resulting memory structure 100, after depositing charge storage layer 90 in vias 80 of FIG. 6 and filling such vias by sacrificial material 105, in accordance with one embodiment of the present invention.

FIG. 10 shows isometric and expanded schematic views of resulting memory structure 100, after slit 108 is formed by excavating sacrificial material 105, in accordance with one embodiment of the present invention.

FIG. 11 shows isometric and expanded schematic views of resulting memory structure 100, after slit 108 is filled by dielectric material 110 and planarized, in accordance with one embodiment of the present invention.

FIG. 12 shows isometric and expanded schematic views of resulting memory structure 100, after the remaining sacrificial material 105 is replaced by conductive material 95, in accordance with one embodiment of the present invention.

FIG. 13 shows a portion of resulting memory structure 100 with the passivation layer and dielectric layers 20 and 110 are removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory arrays.

FIG. 14 shows isometric and expanded schematic views of resulting memory structure 100, after cavities in trench 40 are filled by sacrificial material 42 and removal by anisotropically etch from the sidewalls of trenches 40, instead of deposition of heavily-doped silicon material 50 (e.g., as described in conjunction with FIG. 3), in accordance with one embodiment of the present invention.

FIG. 15 shows isometric and expanded schematic views of resulting memory structure 100, after vias 80 are filled by conductive material 95 and planarized or etched-back, in accordance with one embodiment of the present invention.

FIG. 16 shows isometric and expanded schematic views of resulting memory structure 100, after heavily-doped silicon material 50 and conductive material 60 are deposited to replace sacrificial layer 42, in accordance with one embodiment of the present invention.

FIG. 17 shows a portion of resulting memory structure 100 with the passivation layer and dielectric layers 20 and 70 removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory arrays.

FIG. 18 shows isometric and expanded schematic views of resulting memory structure 100, after forming vias 80 and depositing charge-storage layer 90 and conductive material 95, prior to formation of trenches 40, in accordance with one embodiment of the present invention.

FIG. 19 shows isometric and expanded schematic views of resulting memory structure 100, after formation of trenches 40 and depositions of heavily-doped silicon material 50 and conductive material 60, in accordance with one embodiment of the present invention.

FIG. 20 shows an isometric schematic view of resulting memory structure 100, after deposition of dielectric material 70 into trenches 40, in accordance with one embodiment of the present invention.

FIG. 21 shows isometric and expanded schematic views of resulting memory structure 100, after forming vias 80, in accordance with one embodiment of the present invention.

FIG. 22 shows isometric and expanded schematic views of resulting memory structure 100, after a separation etch removes at least component charge-trapping layer 90 b from the sidewalls of vias 80, in accordance with one embodiment of the present invention.

FIG. 23 shows isometric and expanded schematic views of resulting memory structure 100, after deposition of conductive material 95 to vias 80, in accordance with one embodiment of the present invention.

FIG. 24 shows isometric and expanded schematic views of resulting memory structure 100, after an anisotropic etch removes excess conductive material 60 from trenches 40, in accordance with one embodiment of the present invention.

FIG. 25 shows a portion of resulting memory structure 100 of FIG. 24, with the passivation layer and dielectric layers 20 and 110 removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory arrays.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1. Forming Common Source Line and Common Drain Line (“Common Bit Line”) Prior to Forming Local Word Lines

Initially, a stack of alternately and successively deposited layers of a dielectric material (“dielectric layer”)—e.g., silicon oxide or silicon nitride—and a semiconductor material (e.g., silicon) are provided on top of a planar surface of a semiconductor substrate. The semiconductor material (“silicon layers”) is designed to provide the channel regions of thin-film transistors in a NOR memory array to be formed. Adjacent silicon layers are isolated from each other by the dielectric layer between them. In one embodiment, the stack of silicon and dielectric materials may be annealed at 600° C. for 12 hours to crystallize the deposited silicon material, so as to obtain low-defect grains that provide high carrier mobility. FIG. 1 shows isometric and expanded schematic views of memory structure 100, after patterning and etching of hard mask 30 provided on top of memory structure 100, in accordance with one embodiment of the present invention. Hard mask layer 30 is provided on top of memory structure 100 to provide mechanical stability. As shown in FIG. 1, memory structure 100 represents a resulting structure formed by photolithographically patterning and etching hard mask layer 30 formed on top the multiple alternating silicon and dielectric layers. The etching step divides the silicon and dielectric layers into multiple stacks (“active stacks”), with adjacent active stacks being separated by one of trenches 40.

To facilitate this detailed description, as indicated in FIG. 1, a rectilinear coordinate system is adopted, in which a normal to the planar surface of semiconductor substrate 5 is designated the Z-direction (or “vertical direction”), and two mutually orthogonal directions—each being also orthogonal to the Z-direction—are designated the X- and Y-directions, respectively. The X- and Y-directions. Relative to the Z-direction, the X- and Y-directions are each referred to as a “horizontal” direction.

In one embodiment, 48 silicon layers are deposited, with each silicon layer and each dielectric layer being, for example, 30-nm thick, so that the total thickness of all the silicon and dielectric layers reaches approximately 2.88 microns. (Of course, these values are illustrative; any suitable thickness and any suitable number of layers may be used.) Silicon layers 10 may be formed from a lightly-doped p-type silicon (e.g., with an active carrier concentration between 1×10¹⁷ cm³ and 5×10¹⁸ cm⁻³). In other embodiments, silicon layers 10 may be intrinsic, as deposited, or may be n⁻-doped. Silicon layers 10 and dielectric layers 20 may each be deposited using any suitable technique (e.g., chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD)). Hard mask layer 30 may be formed out of silicon oxide-carbide (SiOC) or any suitable material.

In the embodiment of FIG. 1, trenches 40 (e.g., 60-nm wide) may extend along the Y-direction, provided at a 240-nm pitch along the X-direction (i.e., the distance between corresponding edges of adjacent trenches being about 240 nm along the X-direction). With these dimensions, the process module that etches through layers 10 and dielectric layers 20 (48 layers of each material) to form trenches 40 has an aspect ratio of less than 15. Trenches 40 may be etched, for example, using corrosive gases such as fluorine or chlorine.

Thereafter, as shown in FIG. 2, silicon layers 10 may be recessed from trenches 40 using a suitable selective wet or dry (corrosive gas) etch that etches silicon layers 10 more rapidly than it etches dielectric layers 20 or hard mask layer 30 (i.e., an etch that is more selective to silicon oxide or silicon nitride, and silicon oxide-carbide). Suitable wet etch chemistries for this etch include, for example, any ammonium hydroxide-hydrogen peroxide mixture (APM), any potassium hydroxide-hydrogen peroxide mixture, and any tetramethylammonium hydroxide mixture. In the example shown, silicon layers 10 may be recessed 40 nm on each side (i.e., laterally), to leave a 100 nm width along the X-direction, although any suitable width may be used. Suitable selective dry etch chemistries include, for example, any xenon difluoride gas and any hydrogen-bromine-oxygen gas mixture.

Then, heavily-doped silicon 50 (e.g., n⁺-doped or p⁺-doped polysilicon) is deposited in trenches 40, filling the cavities created by recessing silicon layers 10. An isotropic etch may be used, for example, to remove heavily-doped silicon 50 from trenches 40 and to recess heavy-doped silicon 50 from trenches 40 by 10 nm (X-direction), thereby forming cavities. FIG. 3 shows isometric and expanded schematic views of resulting memory structure 100, after deposition and isotropic etching of heavily-doped silicon 50, in accordance with one embodiment of the present invention. In this manner, strips of heavily-doped silicon 50 are formed that extend along the Y-direction. Heavily-doped silicon 50 subsequently provides a common bit line and a common source line for the thin-film storage transistors in each NOR memory string in the 3-D NOR memory array to be formed. Heavily-doped silicon 50 may be deposited using any appropriate technique (e.g., low-pressure CVD (LPCVD)). In one embodiment, heavily-doped silicon layer 50 may be arsenic-doped to a concentration of 1×10²⁰ cm³.

Thereafter, conductive material 60—which may be any appropriate metal, or combination of metals, that can be conformally deposited to good precision—is deposited, thereby filling the cavities in heavily-doped silicon 50. In one embodiment, conductive material 60 may deposited as a titanium nitride (TiN) liner or adhesive layer, followed by a thicker layer of tungsten (W), using ALD, CVD, or a suitable combination of ALD and CVD techniques. Conductive material 60 may then be removed from the sidewalls of trenches 40 using a selective anisotropic dry etch, wet etch, or both. A suitable anisotropic dry etch may include a suitable corrosive gas (e.g., sulfur fluoride (SF₆), nitrogen fluoride (NF₃), or carbon fluoride (CF₄) or any combination of these gases). FIG. 4 shows isometric and expanded schematic views of resulting memory structure 100, after anisotropic etching of conductive material 60, in accordance with one embodiment of the present invention. As shown in FIG. 4, conductive material 60 are formed as metal strips extending along the Y-direction, each metal strip being adjacent and in electrical contact with a correspond strip of heavily-doped silicon 50.

Dielectric material 70 (e.g., a silicon oxide) may be deposited by ALD and planarized by an etch-back step or a chemical-mechanical polishing (CMP) step to fill trenches 40. FIG. 5 shows an isometric schematic view of resulting memory structure 100, after an etch-back or CMP step on dielectric material 70, in accordance with one embodiment of the present invention.

Thereafter, hard mask 30 is patterned and etched to form numerous vias 80 in the active stacks. Vias 80 each cut through every layer of the active stacks in memory structure 100. In one embodiment, each via has an X-Y plane diameter of 120 nm, with at a 160-nm pitch along the Y-direction (i.e., adjacent vias are 160 nm apart—e.g., center-to-center—along the Y-direction). FIG. 6 shows isometric and expanded schematic views of resulting memory structure 100, after etching of vias 80, in accordance with one embodiment of the present invention. Vias 80 may be etched using substantially the same process steps as those used to form trenches 40. In one embodiment, an acceptance criterion for each 120-nm via (nominally) allows the actual diameter of each via (i.e., its “critical dimension”) to be between 140 nm, at the upper layers of silicon layers 10, and 100 nm, at the lower layers of silicon layers 10).

Thereafter, charge-storage layer 90 may be conformally deposited into each of vias 80. Following deposition of charge-storage layer 90, each via may be filled by deposited conductive material 95 (e.g., a deposited titanium nitride liner, followed a deposited tungsten plug). Storage layer 90 may be a multi-layer consisting of: (i) a tunnel dielectric layer (e.g., silicon oxide), (ii) a charge-trapping layer (e.g., silicon nitride), and (iii) a blocking dielectric layer (e.g., a bi-layer of silicon oxide and aluminum oxide). Conductive material 95 in each via provides a local gate electrode, which is common to all storage transistors along the via. FIG. 7 shows isometric and expanded schematic views of resulting memory structure 100, after vias 80 is filled by conductive material 95, in accordance with one embodiment of the present invention. Storage layer 90 and conductive material 95 may each be deposited using any appropriate technique (e.g., LPCVD, ALD, CVD, or PECVD).

Hard mask 30 may then be removed and replaced by a passivation layer. FIG. 8 shows a portion of resulting memory structure 100 with the passivation layer and dielectric layers 20 removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory arrays. As shown in FIG. 8, in each of silicon layers 10, a portion is bounded on opposite sides by an adjacent pair of lines from heavily-doped silicon 50 (e.g., n⁺-doped). When the transistor is conducting, charge carriers travel between source line and the bit line through channel region 10. The lines of heavily-doped silicon material 50 provide a common bit line and a common source line for the thin-film storage transistors of a NOR memory string extending along the Y-direction. As silicon layers 10 are lightly doped silicon (e.g., p⁻-doped silicon), that portion of each layer of silicon layers 10 bounded by heavily-doped silicon material 50 provides the channel regions of the thin-film storage transistors in the NOR memory string. In addition, silicon layers 10 surround filled vias 80, such that conformal charge-storage layer 90 and conductive material 95 (e.g, a TiN liner surrounding a W plug) within the filled via provide a charge-storage layer and a gate electrode, respectively, for all the thin-film storage transistors formed along the filled via. Acting as shunts, conductive material 60 reduces resistivity in the common source line and the common bit line. In one embodiment, with a nominal 120-nm diameter via at the 160-nm pitch, each thin-film storage transistor may have a channel length of 100 nm, a minimum channel width of 40 nm and a thickness of 30 nm. Relative to the thin-film storage transistors of the 3-D NOR memory array disclosed in the Structural References, the thin-film storage transistors in the NOR memory arrays of the present invention have thicker and wider channel regions, which enable higher “on” currents. A higher “on” current is beneficial for faster read operations.

As shown in FIG. 8, the channel region of each thin-film storage transistor is substantially horizontal (i.e., parallel to the planar surface of semiconductor substrate 5) and its corresponding gate electrode (“local word line”) is the vertical conductor in the adjacent one of vias 80. In this embodiment, as shown in FIG. 8, each thin-film storage transistor has two semi-annular charge-storage sections in charge storage layer 90 surrounding its local word line. By providing two semi-annular storage sections to each thin-film storage transistor, variations in the threshold voltages (Vt) among the thin-film storage transistors of the 3-D NOR memory array is reduced, as the two semi-annular sections both increase its total charge stored and average any shift in the thin-film storage transistor's threshold voltage. The greater charge storage capacity in charge-storage layer 90 also reduces threshold voltage variations.

To route word line signals to the local word lines (e.g., between voltage sources formed in the semiconductor substrate and the local word lines), a set of global word lines may be provided either above or below memory structure 100. (Of course, providing global word lines both above and below the 3-D NOR memory array provides even greater flexibility at a higher cost in terms of additional masking and processing steps.) When the global word lines are formed above the 3-D NOR memory arrays, a temperature-sensitive conductor (e.g., copper) that has a lower resistivity may be selected for the global word lines. Such a material may be selected because global word lines above memory structure 100 does not experience the high temperature cycles during fabrication of underlying memory structure 100. In contrast, when global word lines are formed beneath memory structure 100, a more temperature-tolerant material (e.g., tungsten) would have to selected to avoid any deleterious effect from the temperature cycles. (Tungsten, of course, is known to have a higher resistivity than copper.) Furthermore, global word lines formed above memory structure 100 often may be formed with fewer process steps than if the global word lines are formed beneath the 3-D NOR memory array.

Relative to the processes in the Related Applications, the types of etching steps required steps for processes of the present invention are fewer. In the embodiments described above, etching is required only for silicon layers 10, heavily-doped silicon material 50, conductive material 60, and dielectric layers 20. For example, forming trenches 40 and vias 80 involve only etching of silicon layers 10 and dielectric layers 20. In some of the process steps disclosed in the Related applications, for example, forming similar trenches or vias may involve the complexity of etching steps four or more materials.

In some embodiments, greater storage density may be achieved by designating each of the two semi-annular sections of charge storage layer 90 a portion of a different thin-film storage transistor. According to this approach, following the deposition of charge storage layer 90, rather than filling vias 80 with conductive material 95 (e.g., as shown in FIG. 7 above), sacrificial material 105 (e.g., silicon oxide (SiO₂)) may be deposited instead. FIG. 9 shows isometric and expanded schematic views of resulting memory structure 100, after depositing charge storage layer 90 in vias 80 of FIG. 6 and filling the vias by sacrificial material 105, in accordance with one embodiment of the present invention.

Thereafter, slit 108 (e.g., 40 nm×120 nm) are patterned and etched in each via to remove a portion of sacrificial material 105. using an anisotropic etch (e.g., a fluorocarbon gas and hydrogen), and then to remove a portion of charge storage layer 90 (e.g., a hot phosphoric acid (H₂PO₄)). Significant portions of charge storage layer may remain in each semi-annular section. The charge-storage layer etch need not remove the component tunnel dielectric layer. FIG. 10 shows isometric and expanded schematic views of resulting memory structure 100, after slit 108 is formed by excavating sacrificial material 105 from slits 108, in accordance with one embodiment of the present invention.

Slit 108 may then be filled by dielectric material 110 (e.g., silicon nitride (SiN)), which is preferably a material that has different etching characteristics than sacrificial material 105. FIG. 11 shows isometric and expanded schematic views of resulting memory structure 100, after slit 108 is filled by dielectric material 110 and planarized, in accordance with one embodiment of the present invention.

The remaining sacrificial material 105 may then be removed from each via using, for example, a wet etch (e.g., hydrofluoric acid (HF)) and replaced by a deposition of conductive material 95. FIG. 12 shows isometric and expanded schematic views of resulting memory structure 100, after the remaining sacrificial material 105 is replaced by conductive material 95, in accordance with one embodiment of the present invention. Hard mask 30 may then be removed and a passivation layer may be deposited on top of memory structure 100.

FIG. 13 shows a portion of resulting memory structure 100 with the passivation layer and dielectric layers 20 and 110 removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory arrays. As shown in FIG. 13, the thin-film transistor with the two semi-annular sections in charge storage layer 90 is now divided into two independent thin-film storage transistors, each with one of the two semi-annular sections for charge storage.

2. Forming Common Source Line and Common Bit Line after Forming Local Word Lines; First Option:

In the embodiments described above, heavily-doped silicon material 50—which forms the common source line and the common bit line of the thin-film storage transistors in a NOR memory string of the 3-D NOR memory array—are deposited in memory structure 100 prior to the subsequent process steps for local word line formation (e.g., process steps described in conjunction with FIGS. 6-7 or FIGS. 9-12). As the process steps for local word line formation may require a relatively high temperature, heavily-doped silicon material 50 may be restricted to use dopants of low diffusivity (e.g., arsenic) to avoid dopant diffusion into other layers (e.g., silicon layers 10). However, this restriction may be relaxed in processes according to other embodiments of the present invention in which heavy-doped silicon material 50 (i.e., the common source line and the common bit line) are deposited after local word lines formation.

Processes that deposit heavy-doped silicon material 50 subsequent to local word line formation avoid dopant diffusion from heavily-doped silicon material 50 into at other layers (e.g., silicon layers 10) during the elevated temperatures used in fabricating the local word lines. The reduced risk of dopant diffusion allows for narrower common bit lines and common source lines, and allows dopants of higher diffusivity (e.g., phosphorus) to be used. According to one embodiment of the present invention under this alternative approach, instead of depositing heavily-doped silicon material 50 and conductive material 60, as described in conjunction with FIGS. 3-4 above, sacrificial material 42 (e.g., LPCVD silicon nitride (SiN)) is deposited instead to fill the cavities created by recessing silicon layers 10. FIG. 14 shows isometric and expanded schematic views of resulting memory structure 100, after cavities in trench 40 are filled by sacrificial material 42 and anisotropically removed from the sidewalls of trenches 40, in accordance with one embodiment of the present invention.

The subsequent process steps carry out: (i) filling trenches 40 with dielectric material 70 (e.g., silicon oxide) and (ii) forming the local word lines in substantially the same manner as described above in conjunction with FIGS. 5-7. FIG. 15 shows isometric and expanded schematic views of resulting memory structure 100, after vias 80 are filled by charge storage layer 90 and conductive material 95, and planarized or etched-back, in accordance with one embodiment of the present invention. Under this approach, as heavily-doped silicon material 50 for forming the common source line and the common bit line is not present during the elevated temperature process steps in local word line formation, the concern regarding dopant diffusion into silicon layers 10 is alleviated. Furthermore, as in the embodiments discussed earlier, higher density thin-film storage transistors may be achieved using the techniques illustrated in conjunction with FIGS. 9-13 in which each thin-film storage transistor has a single semi-annular charge-storage region.

After forming the local word line, one or more slits (not shown) may be anisotropically etched in memory structure 100, each slit extending along the X-direction, cutting through every layer of sacrificial material 42 in order to provide access to sacrificial material 42. Alternatively, the slits may be cut in trenches 40 by removing dielectric material 70. Accessing from the slits, sacrificial layer 42 may be removed using a selective etch (e.g., hot phosphoric acid (H₃PO₄)). Hot phosphoric acid etches silicon nitride at a significantly higher than rate than either silicon or silicon. Thereafter, heavily-doped silicon material 50 may be conformally deposited to line the cavities vacated by sacrificial layer 42's removal. Conductive layer 60 may then be deposited to provide the common source line and the common bit line of the thin-film storage transistors, as discussed above. Excess conductive material 60 and heavily doped silicon 50 may be removed from the slits by either a dry etch or a wet etch. The slits may then be filled with a dielectric material (not shown). FIG. 16 shows isometric and expanded schematic views of resulting memory structure 100, after heavily-doped silicon material 50 and conductive material 60 are deposited to replace sacrificial layer 42, in accordance with one embodiment of the present invention.

Hard mask 30 may then be removed and a passivation layer may be deposited on top of memory structure 100.

Because heavily-doped silicon material 50 lines the cavities vacated by sacrificial material 42 (i.e., sacrificial material 42 is deposited on both the ceiling and the floor of the cavities), thicker silicon layers 10 may be required (e.g., 50 nm, rather than 30 nm). To maintain an aspect-ratio of 15 or less during creation of trenches 40, trenches 40 may be made wider (e.g., 80 nm, at a 260-nm pitch).

FIG. 17 shows a portion of resulting memory structure 100 with the passivation layer and dielectric layers 20 and 70 removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory array. As shown in FIG. 17, two annular lines of heavily-doped silicon material 50 (e.g., n⁺-doped)—each extending in the Y-direction and surrounding a core of conductive material 60 (e.g., TiN/W)—are contacting opposite sides of a portion of silicon layers 10 (e.g., p⁻-doped silicon). In this manner, heavily-doped silicon material 50 in each line provides either a common bit line or a common source line for the thin-film storage transistors of a NOR memory string. Acting as shunts, the enclosed core of conductive material 60 in each line reduces the resistivity of the common source line or the common bit line. The portion of silicon layer 10 provides channel region of a thin-film storage transistor. The portion of silicon layer 10 surrounds one of filled vias 80, such that charge-storage layer 90 (e.g., multi-layer of silicon oxide-silicon nitride-silicon oxide-aluminum oxide) and conductive material 95 (e.g, TiN liner surrounding a tungsten plug) within the filled via provide the charge storage layer and the gate electrode, respectively, for the thin-film storage transistors along the length of the filled via. The device structure of the thin-film storage transistor illustrated in FIG. 17 has all the advantages of the device structure of the thin-film storage transistors illustrated in FIG. 8, in addition to other advantages.

3. Forming Local Word Lines Prior to Forming Common Source Line and Common Bit Line; Second Option:

In the embodiments described in detail above, the process sequence for forming the local word lines (e.g., as described in conjunction with described in conjunction with FIGS. 6-7) are carried out after the process sequence that (i) forms trenches 40, recesses silicon layers 10, (ii) deposits heavily-doped silicon material 50 (or, alternatively sacrificial layer 42), (iii) deposits conductive material 60, and (iv) fills trenches 40 with dielectric material 70 (e.g., as described in conjunction with FIGS. 1-5). The order of carrying out these sequences may be reversed.

As discussed above, forming the local word lines prior to providing the heavily-doped silicon material 50 (i.e., the common source line and the common bit line) avoids excessive diffusion of dopants from heavy-doped silicon material 50 during elevated temperature steps associated with local word line formation. For n⁺-doped silicon material, one is not constrained to low-diffusivity dopants (e.g., arsenic), and may select dopants of higher diffusivity (e.g., phosphorus). In addition, conductive material 95 filling vias 80 provides mechanical support to memory structure 100 during and after formation of trenches 40. Consequently, higher aspect-ratio etching steps may be used to form trenches 40. These higher aspect-ratio etching steps allow memory structure 100 to have many more alternating layers of silicon and dielectric materials in the active stack (e.g., 96 layers, rather than 48 in one example above) and, consequently, lithographical constraints may be relaxed to allow even finer features. For example, in one embodiment, vias 80 may have a diameter of 100 nm and placed 180 nm center-to-center apart (i.e., relaxed from a 120-nm diameter, placed 240 nm apart).

After the initial steps of (i) successively and alternately depositing 48 or 96 dielectric layers (e.g., dielectric layers 20) and 48 or 96 silicon layers (e.g., silicon layers 10) on the planar surface of semiconductor substrate 5, and (ii) providing hard mask layer 30, as described above, hard mask layer 30 is patterned and etched to create vias 80. In one embodiment, the silicon layers and the dielectric layer layers are each 30-nm thick. (Of course, these values are provided purely for illustration; any suitable thickness and any suitable number of layers may be used.)

Thereafter, conformal deposition of charge storage layer 90 and deposition of conductive material 95 in bulk (e.g., in the form of a plug) are carried out in substantially the same manner as described above in conjunction with FIGS. 6-7. Under this approach, vias 80 may have a diameter of 100 nm, at a 140 nm pitch (center-to-center along the Y-direction). FIG. 18 shows isometric and expanded schematic views of resulting memory structure 100, after forming vias 80 and depositing conformally charge-storage layer 90, followed by depositing conductive material 95 in bulk, prior to forming trenches 40, in accordance with one embodiment of the present invention. As discussed above, even higher density thin-film storage transistors may be achieved using the techniques illustrated in conjunction with FIGS. 9-13 to provide thin-film storage transistors having charge-storage regions with single semi-annular charge-storage regions.

After the local word lines are formed, the steps of creating trenches 40, recessing silicon layers 10, providing heavily-doped silicon material 50, and providing conductive material 60 may be carried out in substantially the same manner as described above in conjunction with FIGS. 1-5. As the high temperature steps in local word line formation are carried out before heavily-doped silicon material 50 is deposited, there is no need to use sacrificial layer 42 to stand-in for heavily-doped silicon material 50.

Because of greater mechanical stability is achieved by having a plug of conductive material 95, e.g., tungsten, trenches 40 may be 100-nm wide along the X-direction, at a 180-nm pitch. The resulting widths (i.e., along the X-direction) for the channel region, the common bit line, and the common source line are, respectively, 50 nm, 30 nm and 30 nm. The width of conductive material 60 adjacent the common bit line or the common source line may be as little as 10 nm. FIG. 19 shows isometric and expanded schematic views of resulting memory structure 100, after formation of trenches 40 and depositions of heavily-doped silicon material 50 and conductive material 60, in accordance with one embodiment of the present invention.

Trenches 40 may then be filled using dielectric material 70 described above. FIG. 20 shows resulting memory structure 100, after deposition of dielectric material 70 into trenches 40, in accordance with one embodiment of the present invention. The resulting device structure for the thin-film storage transistors of the present invention is substantially as described above in conjunction with FIG. 8.

If the number of silicon layers 10 in the active stack is 96, rather than 48, trenches 40 may be formed in two trench-etching sequences, with the trenches created in the first trench-etching sequence oxide-filled to provide mechanical support while carrying out the second trench-etching sequence. Such an approach is disclosed in some examples in the Related Applications.

4. Forming Local Word Lines Prior to Forming Common Source Line and Common Bit Line; Third Option—Recessed Charge-Trapping Layer:

In the embodiments described above, the component charge-trapping layer within charge-storage layer 90 is continuous between vertically adjacent thin-film storage transistors formed within each one of vias 80. Consequently, charge stored in a thin-film storage transistor may leak into one of its neighbor thin-film storage transistor through the charge-trapping layer. This condition may be avoided if the component charge-trapping layers of vertically adjacent thin-film storage transistors in a via are separated. This result may be achieved by providing the charge-trapping layer of a thin-film storage transistor in a recess of a channel region of the thin-film storage transistor and removing from the via any charge-trapping layer material between thin-film storage transistors.

According to one embodiment of the present invention, the 96-layer active stack of alternating silicon and dielectric materials (e.g., 30-nm thick p⁻-doped silicon layers 10 and 25-nm thick dielectric layer 20), and hard mask layer 30 on top of the active stack may be prepared over a planar surface of semiconductor substrate 5 in substantially the same manner as described above. Thereafter, vias 80 (e.g., 80 nm X-Y plane diameter, at a 140-nm pitch) are etched. Vias 80 has a depth (i.e., in the Z-direction) that extends the full thickness (e.g., 2.64 μm) of the active stack. In one embodiment, 110-nm critical dimensions at the top layers and 90-nm critical dimensions at the bottom layers may be targeted. FIG. 21 shows isometric and expanded schematic views of resulting memory structure 100, after forming vias 80, in accordance with one embodiment of the present invention.

An isotropic etch that is selective to dielectric layers 20 then recesses silicon layers 10 by, for example, 5 nm, although any suitable recess amount (e.g., 10 nm or 20 nm) may be used, forming ledges of dielectric layers 20 between each of silicon layers 10. Component tunnel dielectric layer 90 a and charge-trapping layer 90 b of charge-storage layer 90 are then successively and conformally deposited into vias 80, followed by a separation etch that removes at least deposited charge-trapping layer 90 b from the sidewalls of vias 80. FIG. 22 shows isometric and expanded schematic views of resulting memory structure 100, after a separation etch removes at least component charge-trapping layer 90 b from the sidewalls of vias 80, in accordance with one embodiment of the present invention.

Component blocking dielectric layer 90 c of charge-storage layer 90—consisting, for example, of a silicon oxide layer and an aluminum oxide layer—is then deposited. Conductive material 95—consisting, for example, of a titanium nitride liner surrounding a tungsten plug—fills vias 80. FIG. 23 shows isometric and expanded schematic views of resulting memory structure 100, after deposition of conductive material 95 to vias 80, in accordance with one embodiment of the present invention.

Alternatively, for even higher density thin-film storage transistors, the techniques illustrated in conjunction with FIGS. 9-13 under the single-annular charge-storage region approach may be applied.

Thereafter, trenches 40 may be etched. In one embodiment, trenches 40 are each 80-nm wide, cut at a 220-nm pitch, such that each active stack is 140-nm wide along the X-direction, so as to obtain an aspect ratio of less than 19.0. (With the tungsten plugs in vias 80, reliable etch with an aspect ratio of 26.0 may be achieved). Accessing from trenches 40, an isotropic etch may be used to recess silicon layers 10 by 40 nm along the X-direction on each side, such that each recessed layer of silicon layers 10 may be about 60 nm wide. Heavily-doped silicon material 50, and conductive material 60, each 20 nm wide along the X-direction, may be deposited in substantially the same manner as described above in conjunction with FIGS. 3-4. FIG. 24 shows isometric and expanded schematic views of resulting memory structure 100, after an anisotropic etch removes excess conductive material 60 from trenches 40, in accordance with one embodiment of the present invention.

Trenches 40 may then be filled by dielectric material 70, in the manner substantially as described above in conjunction with FIG. 5. Hard mask 30 may then be removed and a passivation layer may be deposited on top of memory structure 100. In one embodiment, a thin-film storage transistor has a channel length of about 86 nm and a channel width of about 30 nm.

FIG. 25 shows a portion of resulting memory structure 100 with the passivation layer and dielectric layers 20 and 110 removed, so as to illustrate the device structures of the thin-film storage transistors in the 3-D NOR memory arrays. As shown in FIG. 25, each 40-nm wide recessed layer of silicon layers 10 is bounded on opposite sides by adjacent 20-nm layers of heavily-doped silicon material 50; the recessed layer of silicon layers 10 and its bordering heavily-doped silicon material 50 providing a channel region, a common bit line and a common source line for the thin-film storage transistors of a NOR memory string. Conductive material 60 act as shunts to reduce resistivity in the common source line and the common bit line. Conformal charge-storage layer 90—with its recessed component charge-trapping layer 90 b—and conductive material 95 (e.g, a TiN liner surrounding a tungsten plug) within the filled via provide a charge-storage layer and a local word line, respectively, for all the thin-film storage transistors formed along the filled via.

In addition to the higher charge-storage integrity due to the recessed component charge-trapping layer in the charge-storage layer, the thin-film storage transistor of FIG. 25 has the advantage of having an option to use a high-diffusivity dopant (e.g., phosphorus) in heavily-doped silicon material 50, it being deposited after formation of the local word line. The higher quality of silicon layers 10 due to crystallization by annealing at a relatively low temperature (e.g. 600° C.) enables higher “on” currents for faster read operations. Having the greater charge storage capacity in two semi-annular charge-storage sections in each thin-film storage transistor, variations in threshold voltages (Vt) among the thin-film storage transistors are reduced. The device structure of FIG. 25 is also amenable to simpler routing of the global word lines, so that the number of required masking steps is reduced relative to the NOR memory arrays disclosed in the Structural References. These global word lines may be formed above memory structure 100 to take advantage of lower resistivity material that is a feasible option only when fabricated above the memory array.

The detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims. 

We claim:
 1. A thin-film storage transistor formed above a planar surface of a semiconductor substrate, comprising: first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; a first semiconductor layer of a first conductivity having an opening therein; second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers.
 2. The thin-film storage transistor of claim 1, further comprising second and third conductors adjacent and in electrical contact with the second and third semiconductor layers, respectively.
 3. The thin-film storage transistor of claim 1, wherein the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor.
 4. The thin-film storage transistor of claim 1, wherein the charge-storing layer comprises a tunnel dielectric layer, a charge-trapping layer and a blocking dielectric layer.
 5. The thin-film storage transistor of claim 4, wherein the blocking dielectric layer comprises silicon oxide and aluminum oxide.
 6. The thin-film storage transistor of claim 4, wherein the tunnel dielectric layer and the charge trapping-layer are provided as part of the planar layer of materials between the first and second dielectric layers.
 7. The thin-film storage transistor of claim 1, wherein the charge storage layer surrounds the first conductor.
 8. The thin-film storage transistor of claim 1, wherein the charge storage layer is one of two isolated charge-storage sections within the opening each in contact with both the first semiconductor layer and the first conductor.
 9. The thin-film storage transistor of claim 3, wherein the first conductor extends along a direction substantially normal to the planar surface of the semiconductor substrate.
 10. The thin-film storage transistor of claim 3 wherein charge carriers in the channel travel substantially parallel to the planar surface of the semiconductor substrate.
 11. The thin-film storage transistor of claim 7, wherein the thin film storage transistor is one of a plurality of like thin-film storage transistors provided one on top of another above the planar surface of the semiconductor layer, and wherein the first conductor of thin-film storage transistor serve as a common gate electrode for the like thin-film storage transistors.
 12. The thin-film storage transistor of claim 3, wherein thin-film storage transistor is one of a plurality of like thin-film transistors located on the same planar layer of materials, and wherein the second semiconductor layers of the like thin-film storage are in electrical contact with each other forming a common source line and wherein the third semiconductor layers of the like thin-film storage are in electrical contact with each other forming a common bit line.
 13. The thin-film transistor of claim 12, further comprising a plurality of global word lines formed above the active layers, wherein word lines signals are communicated exclusively between the first conductors of the like thin-film storage transistors and the global word lines.
 14. A process for forming a memory array over a planar surface of a semiconductor substrate, comprising: providing over the planar surface a plurality of active layers each separated from another by a dielectric layer, each active layer comprising a plurality of sections each having a first semiconductor region of a first conductivity type; providing in each section a charge-storage layer and a conductor by (a) forming a plurality of vias, wherein each via passes through the first semiconductor region of one of the sections in each active layer and the dielectric layers adjacent thereto, wherein each via extends along a direction substantially normal to the planar surface of the semiconductor substrate; (b) forming the charge storage layer conformally over the sidewalls of the via; and (c) forming the conductor by filling the via with a conductive material; and providing in each section second and third semiconductor regions of a second conductivity type, wherein each of the second and third semiconductor region are provided adjacent and in electrical contact with the first semiconductor region of the section.
 15. The process of claim 14, further comprising forming above the active layers a layer of interconnection conductors each connecting to one or more of the conductors in the filled vias.
 16. The process of claim 14, wherein forming the charge storage layer forming the charge storage layer conformally over the sidewalls of the via comprises successively depositing a tunnel dielectric layer, a charge-trapping layer, and a blocking dielectric layer.
 17. The process of claim 16, wherein the blocking dielectric layer comprises silicon oxide and aluminum oxide.
 18. The process of claim 14, wherein the charge-storage layer comprises depositing a tunnel dielectric layer, a charge-trapping layer, and a blocking dielectric layer, and wherein forming the charge storage layer conformally over the sidewalls of the via comprises: from the sidewalls of each via, recessing each first semiconductor region of the active layers using an etchant selective to the dielectric layers to forma a cavity between the dielectric layers adjacent to the first semiconductor region; forming the tunnel dielectric layer by a conformal deposition of a tunnel dielectric material to coat both the sidewalls of the via and the walls of the cavities; forming the charge-trapping layer by a conformal deposition of a charge-trapping material to coat the sidewalls of the via and to fill the cavities; using an anisotropic etch to remove the charge-trapping material from the sidewalls of the via; and forming the blocking dielectric layer by a conformal deposition of a blocking dielectric material.
 19. The process of claim 14, wherein forming the conductor by filling the via with a conductive material comprises: filling the via with a sacrificial material in the via after the charge-storage layer is formed; patterning and removing from the via a portion of the sacrificial material to form a slit that exposes portions of the charge-storage layer; removing the exposed portions of the charge-storage layers to divide the charge-storage layer on the sidewalls of the via into isolated sections; filling the slit with a dielectric material; and removing all remaining sacrificial material from the via; and filling the via with the conductive material.
 20. The process of claim 14, wherein the step of providing in each section the second and third semiconductor regions comprises: forming a plurality of trenches through the active layers and their adjacent dielectric layers, the trenches each extending in depth substantially normal to the planar surface of the semiconductor surface; accessing from the sidewalls of the trenches, recessing the first semiconductor layer from the sidewalls using an etchant selective to the dielectric layers so as to form a plurality of cavities between adjacent dielectric layers; filling the cavities by depositing into the cavities a semiconductor material of the second conductivity type to form the second and third semiconductor regions of each section; and filling the trenches with a dielectric material.
 21. The process of claim 14, wherein the step of providing in each section the second and third semiconductor regions is carried out before the step of providing in each section a charge-storage layer and a conductor, and wherein the second and third semiconductor regions are each arsenic-doped.
 22. The process of claim 14, wherein the third and fourth semiconductor regions are each phosphorus-doped.
 23. The process of claim 14, wherein prior to providing in each section a charge-storage layer and a conductor carrying out the following: forming a plurality of trenches through the active layers and their adjacent dielectric layers, the trenches each extending in depth substantially normal to the planar surface of the semiconductor surface; accessing from the sidewalls of the trenches, recessing the first semiconductor layer from the sidewalls using an etchant selective to the dielectric layers so as to form a plurality of cavities between adjacent dielectric layers; and filling the cavities by depositing into the cavities a sacrificial material; and wherein, providing in each section second and third semiconductor regions of a second conductivity type is carried out by replacing the sacrificial material by a semiconductor material of the second conductivity type, subsequent to providing in each section the charge-storage layer and the conductor.
 24. The process of claim 23, wherein the semiconductor material of the second conductivity type is phosphorus-doped. 